Gross margin at 77% is strong but notably below Cadence's 88%+, reflecting the mix shift from the Ansys merger integration. The 10-K describes Synopsys as 'the leader in engineering solutions from silicon to systems' with segments spanning EDA, Design IP, and the newly acquired Simulation & Analysis (S&A) business. The S&A segment from Ansys carries lower margins than pure EDA software, diluting the blended gross margin. Pre-Ansys Synopsys likely operated at 80%+ gross margins on the core EDA franchise.

OCF of $1.5B against $1.3B net income yields a healthy 1.15x ratio, confirming cash earnings exceed GAAP. The subscription-dominant revenue model (time-based licenses with ratable recognition) drives upfront cash collection. However, the ratio is lower than Cadence's 1.55x, likely reflecting the impact of Ansys integration costs and the transition of Ansys perpetual licenses to subscription, which temporarily depresses cash collection relative to recognized revenue.

Revenue of $7.1B reflects the combined Synopsys + Ansys entity. The 10-K notes Synopsys changed its fiscal year end to October 31 (from the Saturday nearest October 31), creating minor comparability issues. The revenue base is now diversified across EDA, Design IP, and S&A — with AI chip design, automotive, aerospace/defense, and energy as key verticals. Scale provides R&D leverage and customer cross-sell opportunities.

Synopsys is the other half of the EDA duopoly with Cadence. The 10-K states Synopsys is 'a global leader in supplying the mission-critical EDA solutions that engineers use to design and test integrated circuits.' The duopoly is structurally unassailable: decades of accumulated IP, verified design flows used by every major chip company, and verification libraries that represent billions of engineering hours. No startup or tech giant has cracked this duopoly despite decades of effort.

The Ansys merger extends Synopsys from chip design to full system simulation. The 10-K describes Ansys solutions as 'widely used by engineers, designers, researchers and students across aerospace and defense, automotive, energy, industrial equipment, materials and chemicals, consumer products, healthcare and construction.' This creates cross-sell opportunities: semiconductor customers already using Synopsys EDA can now access system-level simulation from the same vendor, deepening lock-in.

The 10-K highlights Synopsys is 'pioneering artificial intelligence (AI) driven chip design across the full-stack EDA suite to improve efficiency and accelerate the design, verification testing and manufacturing of advanced digital and analog chips.' Synopsys.ai is positioned as the industry's first full-stack AI-driven EDA suite. This AI integration deepens switching costs — customers training AI models on their design data within the Synopsys ecosystem creates proprietary lock-in.

Like Cadence, Synopsys benefits from near-absolute switching costs in core EDA. Chip design teams build entire methodologies, custom scripts, and verification environments around Synopsys tools. The addition of Ansys creates a second layer of switching cost — system-level simulations calibrated to specific product designs become embedded in engineering workflows. The combination of chip-level and system-level lock-in makes the moat wider than either company alone.

FCF of $1.3B represents an 18.3% FCF margin — healthy but significantly below Cadence's 30%. The lower margin reflects Ansys integration costs, transaction-related expenses, and the larger cost structure of the combined entity. As Ansys synergies materialize and one-time costs roll off, FCF margin should converge toward the mid-20%+ range over the next 2-3 fiscal years.